bus

architecture One of the sets of conductors (wires, PCB

tracks or connections in an integrated circuit) connecting

the various functional units in a computer. There are

busses both within the CPU and connecting it to external

memory and peripheral devices. The data bus, address bus

and control signals, despite their names, really constitute a

single bus since each is useless without the others.

The width of the data bus, i.e. the number of parallel

connectors, and its clock rate determine its data rate (the

number of bytes per second which it can carry). This is one

of the factors limiting a computer's performance. Most

current microprocessors have 32-bit busses both internally

and externally. 100 or 133 megahertz bus clock rates are

common. The bus clock is typically slower than the processor

clock.

Some processors have internal busses which are wider than

their external busses (usually twice the width) since the

width of the internal bus affects the speed of all operations

and has less effect on the overall system cost than the width

of the external bus.

Various bus designs have been used in the PC, including

ISA, EISA, Micro Channel, VL-bus and PCI. Other

peripheral busses are NuBus, TURBOchannel, VMEbus, MULTIBUS and

STD bus.

Some networks are implemented as a bus at the physicallayer, e.g. Ethernet - a one-bit bus operating at 10 (or

later 100) megabits per second.

The term is almost certainly derived from the electrical

engineering term "bus bar" - a substantial, rigid power supply

conductor to which several connections are made. This was

once written "'bus bar" as it was a contraction of "omnibus

bar" - a connection bar "for all", by analogy with the

passenger omnibus - a conveyance "for all".

More on derivation.

(2000-03-20)